Method for fabricating junctionless transistor

ABSTRACT

A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of prior U.S. application Ser. No.13/242,861, filed Sep. 23, 2011, now U.S. Pat. No. ______. The entiredisclosure of U.S. application Ser. No. 13/242,861 is hereinincorporated by reference.

FIELD OF THE INVENTION

The present invention generally relates to the field of semiconductors,and more particularly relates to junctionless transistors.

BACKGROUND OF THE INVENTION

Junctionless transistors have been proposed as an alternative toconventional MOSFET transistors for future CMOS technology. However, onedisadvantage of conventional junctionless transistors is that theysuffer from poor short-channel control.

SUMMARY OF THE INVENTION

One embodiment discloses a method for fabricating a transistor. Themethod comprises forming a doped material layer on a semiconductorlayer. Dopant from the doped material layer is diffused into thesemiconductor layer so as to form a graded dopant region in thesemiconductor layer. The graded dopant region has a higher dopingconcentration near a top surface of the semiconductor layer and a lowerdoping concentration near a bottom surface of the semiconductor layer,with a gradual decrease in the doping concentration. The doped materiallayer is removed. After removing the doped material layer, a gate stackis formed on the semiconductor layer. Source and drain regions areformed adjacent to an active area that is in the semiconductor layerunderneath the gate stack. The active area comprises at least a portionof the graded dopant region. The source and drain regions and the activearea have the same conductivity type.

Other objects, features, and advantages of the present invention willbecome apparent from the following detailed description. It should beunderstood, however, that the detailed description and specificexamples, while indicating various embodiments of the present invention,are given by way of illustration only and various modifications maynaturally be performed without deviating from the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 6 are cross-sectional views of a process for forming ajunctionless transistor with a graded dopant region according to oneembodiment of the present invention;

FIG. 7 is a cross-sectional view of a junctionless transistor with agraded dopant region according to another embodiment of the presentinvention;

FIGS. 8 and 9 are cross-sectional views of a fully depleted surfacechannel transistor and a junctionless transistor integrated on the samechip according to one embodiment of the present invention;

FIG. 10 is an operational flow diagram illustrating a process forforming a junctionless transistor with a graded dopant region accordingto one embodiment of the present invention;

FIG. 11 is a graph illustrating short channel and long channelperformance of a conventional junctionless transistor; and

FIG. 12 is a graph illustrating short channel and long channelperformance of a junctionless transistor according to one embodiment ofthe present invention.

DETAILED DESCRIPTION

Embodiments of the present invention provide a junctionless transistorand a method for fabricating the same. The junctionless transistor ofthe present invention provides improved short channel control ascompared to conventional junctionless transistors. FIG. 11 shows asimulation of a conventional P-channel field-effect transistor (PFET)with uniform channel doping. The lower curve 1102 represents a longchannel device with a gate length of 500 nm, a uniform channel doping of5E19/cm3, and a silicon-on-insulator (SOI) thickness of 6 nm. As shown,the device functions well with a long channel of 500 nm. However, whenthe gate length is scaled to 26 nm this conventional junctionlesstransistor exhibits very poor short channel control, as shown by theupper curve 1104. In fact, this conventional junctionless transistorperforms more like a resistor (i.e., no on or off state) with respect toshort channel. The junctionless transistor of the present invention, onthe other hand, provides for much improved short channel control, asshown in the simulation of FIG. 12. The upper curve 1204 for a shortchannel device shows a five order of magnitude difference between the onand off states of the device.

FIGS. 1 to 6 illustrate a process for forming a junctionless transistorwith localized and graded channel doping according to one embodiment ofthe present invention. As shown in FIG. 1, there is provided an SOIwafer having a silicon substrate 102, a buried insulator layer (e.g.,buried oxide “BOX” 104, and an extremely thin silicon-on-insulator(ETSOI) layer 106. The ETSOI layer 106 of this embodiment has athickness ranging from about 1 nm to 20 nm, while in another embodimentthe ETSOI layer 106 has a thickness ranging from about 3 nm to 10 nm. Inthe illustrated embodiment, the SOI wafer is formed by thinning a“thick” SOI wafer (with a thickness in the 30 nm to 90 nm range) usingoxidation and a hydrofluoric acid (HF) wet etch. The ETSOI layer 106 canbe any semiconducting material, including but not limited to Si(silicon), strained Si, SiC (silicon carbide), Ge (geranium), SiGe(silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Gealloys, GaAs (gallium arsenide), InAs (indium arsenide), InP (indiumphosphide), or any combination thereof.

As shown in FIG. 2, a doped material 208 is formed on exposed surfacesof the ETSOI layer 106. In this embodiment, the doped material 208 isformed through epitaxial growth. When the chemical reactants arecontrolled and the system parameters set correctly, the depositing atomsarrive at the surface of the ETSOI layer 106 with sufficient energy tomove around on the surface and orient themselves to the crystalarrangement of the atoms of the deposition surface. Thus, an epitaxialfilm deposited on a [100] crystal surface will take on a [100]orientation. If, on the other hand, the wafer has an amorphous surfacelayer, the depositing atoms have no surface to align to and formpolysilicon instead of single crystal silicon. Silicon sources for theepitaxial growth include silicon tetrachloride, dichlorosilane(SiH2Cl2), and silane (SiH4). The temperature for this epitaxial silicondeposition is from 550° C. to 900° C.

In the illustrated embodiment, the doped material 208 is formed throughselective-epitaxial growth of SiGe atop the ETSOI layer 106. The Gecontent of the epitaxial grown SiGe ranges from 5% to 60% (by atomicweight). In another embodiment, the Ge content of the epitaxial grownSiGe ranges from 10% to 40%. The epitaxial grown SiGe of the illustratedembodiment is under an intrinsic compressive strain that is produced bya lattice mismatch between the larger lattice dimension of the SiGe andthe smaller lattice dimension of the layer on which the SiGe isepitaxially grown. The epitaxial grown SiGe produces a compressivestrain in the portion of the ETSOI layer 106 in which the channel of asemiconductor device is subsequently formed.

In this embodiment, the doped material 208 is doped with a firstconductivity type dopant during the epitaxial growth process. P-typeMOSFET devices are produced by doping the doped material 208 withelements from group III of the periodic table (e.g., boron, aluminum,gallium, or indium). As an example, the dopant can be boron in aconcentration ranging from 1×10E18 atoms/cm3 to 2×10E21 atoms/cm3.

In another embodiment, the doped material 208 is composed of epitaxiallygrown Si:C (carbon doped silicon). The carbon (C) content of theepitaxial grown Si:C ranges from 0.3% to 10% (by atomic weight). Inanother embodiment, the carbon (C) content of the epitaxial grown Si:Cranges from 1% to 2%. In one embodiment, the epitaxial grown Si:C isunder an intrinsic tensile strain that is produced by a lattice mismatchbetween the smaller lattice dimension of the Si:C and the larger latticedimension of the layer on which the Si:C is epitaxially grown. Theepitaxial grown Si:C produces a tensile strain in the ETSOI layer 208 inwhich the channel of a semiconductor device is subsequently formed. Inthis embodiment, the doped material 208 is doped with a secondconductivity type dopant during the epitaxial growth process. N-typeMOSFET devices are produced by doping the doped material 208 withelements from group V of the periodic table (e.g., phosphorus, antimony,or arsenic).

Alternatively, the doped material 208 is a doped dielectric, forexample, doped oxide, formed by deposition, including but not limitedto, atomic layer deposition (ALD), molecular layer deposition (MLD),chemical vapor deposition (CVD), low-pressure chemical vapor deposition(LPCVD), plasma enhanced chemical vapor deposition (PECVD), high densityplasma chemical vapor deposition (HDPCVD), sub-atmospheric chemicalvapor deposition (SACVD), rapid thermal chemical vapor deposition(RTCVD), in-situ radical assisted deposition, high temperature oxidedeposition (HTO), low temperature oxide deposition (LTO), ozone/TEOSdeposition, limited reaction processing CVD (LRPCVD), ultrahigh vacuumchemical vapor deposition (UHVCVD), metalorganic chemical vapordeposition (MOCVD), molecular beam epitaxy (MBE), physical vapordeposition, sputtering, plating, evaporation, spin-on-coating, ion beamdeposition, electron beam deposition, laser assisted deposition,chemical solution deposition, or any combination of those methods. Inone embodiment, the dopant in the doped material layer 208 is boron,arsenic, phosphorus, or indium, with a concentration ranging from1×10E18 atoms/cm3 to 2×10E21 atoms/cm3.

After the doped material 208 is formed, the dopant is diffused into theETSOI layer 106 to form a graded dopant region 310 within the ETSOIlayer 106, as shown in FIG. 3. In this embodiment, the graded dopantregion 310 spans the entire depth of the ETSOI layer 106. However, inother embodiments, the graded dopant region 310 partially spans thedepth of the ETSOI layer 106. While the illustrated example uses ann-type dopant, the description is also applicable to the use of p-typedopant. The graded dopant region 310 has a higher doping concentrationnear the top surface 312 of the ETSOI layer 106 and a lower dopingconcentration near the BOX layer 104, with a gradual decrease in thedoping concentration. For example, with an ETSOI layer thickness of 6nm, 5E19/cm3 of boron can be localized at the top 2 nm of the ETSOIlayer 106, 1E19/cm3 of boron can be localized in the middle 2 nm of theETSOI layer 106, and 1E16/cm3 of boron, can be localized at the bottom 2nm of the ETSOI layer 106.

In the illustrated embodiment, the dopant from the doped material 208 isdiffused into the ETSOI layer 106 by an annealing processes such asrapid thermal annealing, furnace annealing, flash lamp annealing, laserannealing, or any suitable combination thereof. For example, thermalannealing can be used to diffuse the dopant from the doped material 208into the ETSOI layer 106 at a temperature ranging from about 700° C. to1350° C.

After the graded dopant region 310 is formed within the ETSOI layer 106,etching is performed to remove the doped material 208, as shown in FIG.4. An active area (channel region) 414 for the transistor is thendefined within the ETSOI layer 106 through pad-film deposition,patterning (e.g., by photolithography), and reactive-ion etching (RIE).For example, a pad oxide having a thickness of 2 nm to 10 nm is formedin an oxidation furnace, and a pad nitride is deposited over the padoxide using low-pressure chemical vapor deposition (LPCVD) orrapid-thermal chemical vapor deposition (RTCVD). Photolithography and anitride-oxide-silicon RIE are then performed to define the active area.

Next, the active area 414 is isolated, such as through shallow trenchisolation (STI), Local Oxidation Of Silicon for Isolation (LOCOS), ormesa isolation. In this embodiment, STI is obtained through depositionof an STI oxide, densification anneals, and chemical-mechanicalpolishing (CMP) that stops on the pad nitride. This forms an STI region417 above the BOX layer 104 that is continuous around the active area414. The pad nitride, along with any STI oxide remaining on the padnitride, and the pad oxide are then removed (e.g., through wet etchingusing hot phosphoric acid and HF).

A gate dielectric 518 and a gate conductor 520 are formed on the activeregion 414, as shown in FIG. 5. More specifically, a stack of a gatedielectric layer and a gate conductor layer are formed on the activeregion 414. This stack is then patterned and etched to form the gatedielectric 518 and the overlying gate conductor 520 in a portion of theactive region 414. The gate dielectric 518 of this embodiment is aconventional dielectric material (such as silicon oxide, siliconnitride, silicon oxynitride, or a stack thereof) that is formed bythermal conversion of a top portion of the active region and/or bychemical vapor deposition (CVD). In an alternative embodiment, the gatedielectric 520 is a high-k dielectric material (such as hafnium oxide,zirconium oxide, lanthanum oxide, aluminum oxide, titanium dioxide,strontium titanate, lanthanum aluminate, yttrium oxide, an alloythereof, or a silicate thereof) that is formed by CVD, atomic layerdeposition (ALD), molecular beam epitaxy (MBE), pulsed laser deposition(PLD), liquid source misted chemical deposition (LSMCD), or physicalvapor deposition (PVD). Alternatively, the gate dielectric may compriseany suitable combination of those dielectric materials.

The gate conductor 520 is a semiconductor (e.g., polysilicon) gate layerand/or a metal gate layer. For example, the gate dielectric 518 can be aconventional dielectric material and the gate conductor 520 can be asemiconductor gate layer. Alternatively, the gate dielectric 518 can bea high-k dielectric material and the gate conductor 520 can be a metalgate layer of a conductive refractory metal nitride (such as tantalumnitride, titanium nitride, tungsten nitride, titanium aluminum nitride,triazacyclononane, or an alloy thereof). In a further embodiment, thegate conductor 520 comprises a stack of a metal gate layer and asemiconductor gate layer. In the illustrated embodiment, a gatepolysilicon cap 522 is deposited on the gate conductor layer 520, suchas through LPCVD or silicon sputtering.

A gate spacer layer 524 formed of a dielectric material (such as siliconoxide, silicon nitride, silicon oxynitride, boron nitride, siliconcarbon, or a combination of these) is formed on the sides of the gatestack 518, 520, and 522. In this embodiment, the dielectric layer isformed and then reactive-ion etching is used to remove the dielectricmaterial except from the sidewalls of the gate stack 518, 520, and 522.Alternatively, the gate spacer layer 524 can be allowed to remain on topof the gate stack.

As shown in FIG. 6, source/drain regions 526 and 528 are then formed inthe ETSOI layer 106 on the sides of the gate stack 518, 520, and 522,with the active area 414 remaining between the source/drain regions 526and 528. In this embodiment, source/drain extension regions 527 and 529are formed in the ETSOI layer 106 below the gate sidewall spacers 524.These source/drain extension regions 527 and 529 are shallower in depththan the source/drain regions 526 and 528 and extend from thesource/drain regions 526 and 528 to the active area 414.

In this embodiment, the source/drain regions 526 and 528 and extensionregions 527 and 529 have the same type of dopant as the active area 414.In one embodiment, the source/drain regions 526 and 528 and extensionregions 527 and 529 are further doped using the same doping type as theactive area 414 to lower source/drain resistance. In one embodiment, thesource/drain regions 526 and 528 are further doped by ion implantation,gas phase doping, plasma doping, plasma immersion ion implantation,cluster doping, infusion doping, liquid phase doping, or solid phasedoping. A subsequent anneal is performed (e.g., millisecond laser annealor flash anneal) to provide relatively deep diffusions for the sourceand drain regions 526 and 528. As shown in FIG. 6, the source/drainregions 526 and 528 have a uniform doping concentration while the activearea 414 has a graded doping concentration. After further dopingsource/drain regions 526 and 528, the dopant concentration in thesource/drain region is greater than the dopant concentration in thechannel region.

Next, silicide areas are formed for contacts. In this embodiment, ametal is deposited on top of the source/drain regions 526 and 528, ananneal is performed to form silicide, and then the metal is selectivelyremoved (e.g., through an aqua regia wet etch). For example, the metalis nickel, cobalt, titanium, platinum, or a combination thereof.Conventional fabrication steps are then performed to form the remainderof the integrated circuit that includes this transistor.

In another embodiment, raised source/drain regions are formed, as shownin FIG. 7. In this embodiment, faceted raised source/drain regions 730and 732 are formed using epitaxy to thicken the silicon where deepsource/drain implantation is to be performed in order to reduce theseries resistance and increase the on current. For example, an initialpre-cleaning can be performed using an HF wet etch or HF-vapor basedchemical oxide removal (COR) to expose the silicon surface of thesource/drain regions 526 and 528.

Next, epitaxy that is selective with respect to oxide (and optionallynitride) is used to form the faceted raised source/drain regions 730 and732 that are in-situ doped with the same doping type as the source/drainregions 526 and 528 and the active region 414. In another embodiment,the raised source/drain regions 730 and 732 do not contain any doping.In the illustrated embodiment, the growth rates for [100] versus [110]oriented planes are engineered so that during the epitaxial growth on[100] silicon, faceted raised/source drain regions are obtained.

The faceted raised source/drain regions 730 and 732 have angled(faceted) sides 734 and 736 with an angle from 5 degrees to 85 degrees(relative to the bottom surface of the faceted raised source/drainregion). According to another embodiment, each of the faceted sides 734and 736 has an angle from 40 degrees to 55 degrees. In anotherembodiment, the angle for each of the faceted sides 734 and 736 issubstantially less than 90 degrees and substantially greater than zerodegrees. The angle of one of the sides 734 and 736 can be different thanthe angle of the other. In a further embodiment, non-faceted (i.e.,vertical) raised source/drain regions are formed.

Next, silicide areas 738 and 740 are formed for contacts. In thisembodiment, a metal is deposited on top of the raised source/drainregions 730 and 732, an anneal is performed to form silicide, and thenthe metal is selectively removed. For example, the metal is nickel,cobalt, titanium, platinum, or a combination thereof. Conventionalfabrication steps are then performed to form the remainder of theintegrated circuit that includes this transistor.

In another embodiment of the present invention, fully depleted (FD) CMOSdevices with multi-Vt are formed on the same chip with the junctionlesstransistor. In this embodiment, the FD device is a surface channel FDdevice with an undoped channel, and four threshold voltages (Vts) (2 forNFET and 2 for PFET devices) are achieved by two gate stacks. FIG. 8shows a surface channel FD NFET 801 integrated with a junctionless PFET803. The surface channel FD device 801 is a low-Vt device and thejunctionless device 803 is a regular-Vt device. The active area(channel) of the junctionless device 803 is heavily N-doped with agraded profile as described above. The active area (channel) 815 of thesurface channel FD device 801 is undoped. The gate work function of thejunctionless device 803 is close to P-type Band-edge, and the gate workfunction of the surface channel FD device 801 is close to N-typeBand-edge.

FIG. 9 shows a surface channel FD PFET 901 integrated with ajunctionless NFET 903. The surface channel FD device 901 is a low-Vtdevice and the junctionless device 903 is a regular-Vt device. Theactive area (channel) of the junctionless device 903 is heavily P-dopedwith a graded profile. The active area (channel) 915 of the surfacechannel FD device 901 is undoped. The gate work function of thejunctionless device 903 is close to N-type Band-edge, and the gate workfunction of the surface channel FD device 901 is close to P-typeBand-edge.

The junctionless devices 803 and 903 of FIGS. 8 and 9 are formed usingthe processes described above. For the surface channel FD devices 801and 901, a mask is formed over the ETSOI layer 806 and 906 prior to thedoped material 208 being formed. The mask is a hardmask material such asoxide or nitride. During the formation and dopant diffusion of the dopedmaterial 208 , the surface channel FD devices 801 and 901 are protectedby the mask. After the doped material 208 has been formed and the dopantdiffused into the ETSOI layer of the junctionless devices 803 and 903,the mask is removed and the surface channel FD devices 801 and 901 areformed in tandem utilizing the fabrication steps described above for thejunctionless devices.

FIG. 10 is an operational flow diagram illustrating a process forforming a junctionless transistor according to one embodiment of thepresent invention. A BOX layer 104 is formed on a silicon substrate 102,at step 1004. The BOX layer 104 is formed with a thickness that is lessthan 50nm. An ETSOI layer 106 is formed on the BOX layer 104, at step1006. A doped material 208 is formed on the semiconductor layer 106, atstep 1008. The dopant from the doped material 208 is diffused into theETSOI layer 106 forming a graded dopant region 310, at step 1010.

The doped material 208 is then removed, at step 1012. A gate stack 518,520, and 522 is formed on the semiconductor layer 106, at 814.Source/drain regions 526 and 528 are formed within the ETSOI layer 106on the sides of the gate stack 518, 520, and 522 with the active area414 positioned between the source/drain regions 526 and 528.Source/drain extension regions 527 and 529 are formed within the ETSOIlayer 106 below the gate sidewall spacer 524. The source/drain regions526 and 528, the source/drain extension regions 527 and 529, and theactive area 414 all have the same dopant type.

The source/drain regions 526 and 528 are optionally doped, at step 1016.Raised source/drain regions 730 and 732 are optional formed and dopedwith the same dopant type as the graded dopant region 310, at step 1018.Conventional steps are then performed to complete the fabricationprocess.

The fabrication process described above is also applicable to forming asurface channel FD device. However, an additional step is performed toform a mask over the ETSOI layer of the surface channel FD device priorto step 1008. Then, after step 1010 has been completed, this mask isremoved. The surface channel FD device is formed along with thejunctionless transistor using the remaining steps.

It should be noted that some features of the present invention may beused in an embodiment thereof without use of other features of thepresent invention. As such, the foregoing description should beconsidered as merely illustrative of the principles, teachings,examples, and exemplary embodiments of the present invention, and not alimitation thereof.

It should be understood that these embodiments are only examples of themany advantageous uses of the innovative teachings herein. In general,statements made in the specification of the present application do notnecessarily limit any of the various claimed inventions. Moreover, somestatements may apply to some inventive features but not to others.

The circuit as described above is part of the design for an integratedcircuit chip. The chip design is created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer transmitsthe resulting design by physical means (e.g., by providing a copy of thestorage medium storing the design) or electronically (e.g., through theInternet) to such entities, directly or indirectly. The stored design isthen converted into the appropriate format (e.g., GDSII) for thefabrication of photolithographic masks, which typically include multiplecopies of the chip design in question that are to be formed on a wafer.The photolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

The methods as discussed above are used in the fabrication of integratedcircuit chips.

The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare chip, or in a packaged form. Inthe latter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboard,or other input device, and a central processor.

As required, detailed embodiments of the present invention are disclosedherein; however, it is to be understood that the disclosed embodimentsare merely exemplary of the invention, which can be embodied in variousforms. Therefore, specific structural and functional details disclosedherein are not to be interpreted as limiting, but merely as a basis forthe claims and as a representative basis for teaching one skilled in theart to variously employ the present invention in virtually anyappropriately detailed structure. Further, the terms and phrases usedherein are not intended to be limiting; but rather, to provide anunderstandable description of the invention.

The terms “a” or “an”, as used herein, are defined as one as or morethan one. The term plurality, as used herein, is defined as two as ormore than two. Plural and singular terms are the same unless expresslystated otherwise. The term another, as used herein, is defined as atleast a second or more. The terms including and/or having, as usedherein, are defined as comprising (i.e., open language). The termcoupled, as used herein, is defined as connected, although notnecessarily directly, and not necessarily mechanically. The termsprogram, software application, and the like as used herein, are definedas a sequence of instructions designed for execution on a computersystem. A program, computer program, or software application may includea subroutine, a function, a procedure, an object method, an objectimplementation, an executable application, an applet, a servlet, asource code, an object code, a shared library/dynamic load libraryand/or other sequence of instructions designed for execution on acomputer system.

Although specific embodiments of the invention have been disclosed,those having ordinary skill in the art will understand that changes canbe made to the specific embodiments without departing from the spiritand scope of the invention. The scope of the invention is not to berestricted, therefore, to the specific embodiments, and it is intendedthat the appended claims cover any and all such applications,modifications, and embodiments within the scope of the presentinvention.

What is claimed is:
 1. A method for fabricating a transistor, the methodcomprising: forming a doped material layer on a semiconductor layer;diffusing dopant from the doped material layer into the semiconductorlayer so as to form a graded dopant region in the semiconductor layer,the graded dopant region having a higher doping concentration near a topsurface of the semiconductor layer and a lower doping concentration neara bottom surface of the semiconductor layer, with a gradual decrease inthe doping concentration; removing the doped material layer; after theremoving, forming a gate stack on the semiconductor layer; and formingsource and drain regions adjacent to an active area that is in thesemiconductor layer underneath the gate stack, the active areacomprising at least a portion of the graded dopant region, wherein thesource and drain regions and the active area have the same conductivitytype.
 2. The method of claim 1, further comprising: forming a buriedinsulator layer above a substrate; and forming the semiconductor layeron the buried insulator layer.
 3. The method of claim 1, wherein thediffusing of the dopant comprises performing an anneal.
 4. The method ofclaim 1, further comprising incorporating dopant into the source anddrain regions so as to have a uniform dopant concentration in the sourceand drain regions.
 5. The method of claim 1, wherein the source anddrain regions have a higher dopant concentration than a maximum dopantconcentration in the active area.
 6. The method of claim 1, whereinforming the source and drain regions comprises: forming a gate spacer onsidewalls of the gate stack; and forming raised source and drain regionsadjacent to the gate spacer.
 7. The method of claim 6, furthercomprising: incorporating dopant into the raised source and drainregions so as to have a uniform dopant concentration in the raisedsource and drain regions.